Hitherto, there has been known a system in which different buses such as main bus and sub bus are connected through a bus repeater such as gateway, etc. to carry out DMA transfer of data between these buses by DMA (Direct Memory Access) controller provided in the main bus.
For example, in the configuration as shown in FIG. 1, a main bus 101 and a sub bus 102 are both connected to a bus repeater 103 such as bus gateway, etc. A device 104 such as CPU or various interfaces, etc. and a DMA controller 105 are connected to the main bus 101, and a device 106 and a memory 107 such as ROM, etc. are connected to the sub bus 102.
In the example of FIG. 1, the DMA controller 105 on the main bus 101 also controls the sub bus 102 through the bus repeater 103 to thereby realize DMA transfer, e.g., between the device 104 and the device 106. As stated above, if access times of respective buses are the same order even between different buses 101, 102, efficient data transfer can be carried out without useless wait (standby) time.
Meanwhile, in the case where different buses coexist within one system, there are many instances where bus widths and/or data access speeds are different. For example, in the example of FIG. 1, the main bus 101 has bus width of 32 bits and high data access speed and the sub bus 102 has bus width of 16 bits and low data access speed.
In the case where DMA transfer is caused to be carried out between buses in which bus widths and/or data access speeds are different, there is the drawback that useless wait (standby) time is caused to take place on the high speed bus, e.g., the main bus 101 of FIG. 1.
In view of the above, it is conceivable to connect two different buses through buffer memory to carry out DMA transfer through this buffer memory. In this case, when attempt is made to carry out diagnosis as to whether or not DMA transfer normally functions, it is required to allow CPUs of respective buses to run in debugging mode. This is troublesome.
Moreover, in the case where data transfer has not been normally carried out, since it is considered that there is any defect in CPUs of both buses or diagnostic program, there are many instances where finding of the cause becomes very difficult.
Particularly, in the case where CPU or DMA controller, etc. is provided within one LSI, it takes long development time, and schedule of diagnosis, etc. becomes great problem.
Before LSI is designed or is trially manufactured in practice, software simulation including peripheral equipment is carried out to confirm functions as many as possible. However, because it takes much time in simulation, sufficient verification cannot be carried out and there are actual circumstances where it is required to examine closely the problems in short time after trially manufactured LSI, etc. is made up. Thus, there are many instances where difficulty of debugging as described above results in hindrance of development of product.
Further, in the case where data transfer is carried out between devices, there are arrangements of data convenient for respective devices. To cope with this, it is necessary to round down extra data, or to insert another data into the portion between data trains which have been transferred.
When CPU attempts to carry out an operation as described above with respect to data train developed on the memory, it once reads such data train into the register of the CPU thereafter to have to write it for a second time. For this reason, efficiency is very poor (low). This reduces the time required when CPU attempts to carry out other work, and is not therefore preferable.
Here, it is conceivable that DMA controller changes every time transfer source address or transfer destination address at the time of data transfer. In this case, address of transfer source and list of transfer quantity are prepared and DMA controller carries out DMA transfer in accordance with that list every time. However, CPU must prepare transfer specification table. As a result, there is the difficulty that overhead for checking transfer specification every time takes place, etc.
Moreover, in the case where different buses coexist within one system as described above, there are many instances where bus widths are different. For example, in the example of FIG. 1, the main bus 101 has bus width of 32 bits and high data access speed and the sub bus 102 has bus width of 16 bits and low data access speed. Also in the case where DMA transfer is caused to be carried out between buses where bus widths are different as stated above, there are instances where extra data is rounded down or another data is inserted into the portion between data trains which have been transferred. Also in this case, it is desirable that change of data structure or delimit of address can be carried out with ease.